nSys releases verification IP blocks using openVera hardware verification language

MOUNTAIN VIEW, CA, April 15, 2002 - Netsys Software Pvt. Ltd. (nSys), a solution provider for emerging standards, announced the availability of two OpenVera™ verification intellectual property (IP) offerings that dramatically reduce the verification time of complex system-on-chip (SoC) designs. OpenVera verification IP cuts down verification time by providing a re-useable verification environment, including stimulus generators, protocol monitors and objects for functional coverage analysis.

“We are focused on easing time-to-market pressure on product development teams by reducing their verification time and effort,” said Atul Bhatia, director at nSys. “With OpenVera verification IP, verification engineers can generate stimulus for their SoCs immediately, by instantiating our OpenVera models, saving months of effort in creating and debugging the test environment.”

nSys plans to offer a number of OpenVera verification IP solutions, starting with UART and IEEE 1284, which are commonly used on SoCs. The nSys family of OpenVera verification IP provides a consistent interface for integrating into an SoC verification environment, making it easy for engineers to use multiple OpenVera verification IP solutions in a verification environment.

“nSys is a charter member of the OpenVera Catalyst Program making important contributions to the PC and server markets,” said Jim Watts, OpenVera program manager at Synopsys, Inc. (Nasdaq:SNPS) “A goal of Synopsys’ OpenVera Catalyst Program is to accelerate the availability and proliferation of OpenVera verification IP solutions to enhance verification productivity for our mutual customers. This goal is achieved by active participation from members like nSys.”

The OpenVera verification IP solutions from nSys offer a rich set of features, including:

• Full support of automatic random (including constrained random) and directed testing (including error generation/injection).
• Built-in checking mechanism with on-the-fly protocol checking.
• Built-in monitors.
• Extensive support for functional coverage such as: closed loop testing, cross-coverage based on all the variable parameters and accumulated coverage across multiple simulation runs.
  Scalable architecture for use as standalone test environment or embedding in an SoC environment.
• Programmable message logging capabilities such as ERROR/WARNING/INFO/DEBUG.
• Flexibility for stopping tests based upon packet count, error/warning count, and time.
• Object-oriented architecture to support plug and play use model.
• Support for Verilog as well as VHDL implementations.

For a complete listing of features of the nSys verification IP offerings for OpenVera, visit the nSys website at http://www.nsysinc.com

Availability
The OpenVera verification IP offerings from nSys are immediately available. nSys OpenVera verification IP solutions ship with full documentation and example configurations for SoC verification environments. nSys also offers expert verification consulting services for OpenVera users.

About OpenVera
OpenVera is an open source hardware verification language developed specifically to meet the unique requirements of functional verification. The language enables users to describe the target application environment, including complex protocols and data objects, at a high level of abstraction, which dramatically increases productivity, readability and reusability. The latest OpenVera developments will be featured at the ninth semiannual Synopsys EDA Interoperability Developers’ Forum in Sunnyvale, CA on Tuesday, April 16, 2002. For more information on OpenVera and OpenVera verification IP solutions, visit www.open-vera.com.

About nSys
nSys provides flexible solutions to reduce the time-to-market for its customers by focusing upon time spent during the verification phase of ASIC development. By leveraging its vast experience in standards-based product development for PCs and servers, the nSys team creates verification solutions that solve the most challenging functional verification problems in the world. The nSys solution is in the form of services based on specialized knowledge of standards and tools or services, backed by verification IP developed by nSys. To learn more, visit http://www.nsysinc.com.

Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.