|
|
nSys
announces the release of PCI-X nVS, a verification solution for
PCI-X 2.0 in Verilog
SAN JOSE, Calif.,
August 23, 2003 – Netsys Software Pvt. Ltd. (nSys), a solution
provider for emerging standards, today announced the availability
of PCI-X nVS a verification solution for PCI-X 2.0 in verolig. The
nSys PCI-X verification IP significantly reduces the verification
time for complex system-on-chip (SoC) designs that are using the
PCI-X protocol in market segments, such as desktop, mobile computing,
enterprise and standard servers, as well as embedded and communications
devices.
“Our PCI-X verification
IP enables customers to easily create sophisticated verification
environments that simulate real world applications of PCI-X devices,”
said Atul Bhatia, director at nSys. “As a result, customers
can test the entire functionality of their PCI-X interfaces without
having to write a single line of code.”
Netsys also announced
the availability of three additional verification IPs based on OpenVera
and OVA: UART, Parallel 1284 and PCMCIA. These newly announced verification
IP, together with the UART and IEEE 1284 announced in April 2002,
provide customers a comprehensive OpenVera verification IP solution
for SoCs targeted for the server and PC markets. The nSys family
of verification IP provides a common interface for the immediate
creation of verification environments using multiple IP.
"OpenVera verification
IP solutions enable verification engineers to focus on verifying
their designs rather than investing lots of time setting up sophisticated
verification environments said James Watts, OpenVera program manager
at Synopsys, Inc. (Nasdaq:SNPS) “With these solutions, design
and verification engineers can generate appropriate test scenarios,
as well as check for protocol compliance of their SoCs, reducing
effort in creating and debugging the test environment.”
The PCI-X verification
IP solutions from nSys offer a rich set of features, including:
- Support for different types
of PCI-X modes: Mode 1 Parity, Mode 1 ECC, Mode 2 266 32/64
Bit, Mode 2 533 32/64 Bit
- Tests entire functionality
of an interface without writing a single line of code
- Support for multiple instantiation
to create complex verification environment
- Full support of automatic random,
directed, error and compliance testing
- Generating and driving bus traffic
as a PCI-X Initiator and accepts split completions ??
- Supports all transaction layer,
data link layer and physical layer functionality as defined
in PCI-X specifications version 1.0 ??
- Implements PCI-X configuration
space as defined for end points and express extended capabilities
configuration space registers ??
- Implements PCI-X advanced error
reporting capabilities register in configuration space
- Fully automated flow control
- Implements PCI-X virtual channel
capabilities register
- Support for multiple virtual
channels
- Support for Verilog as well
as VHDL implementations
- Based upon the OpenVera layered
model architecture guidelines
- Consistency of interface, installation,
operation and documentation across nSys family of OpenVera verification
IP
- Extensive support for functional
coverage such as closed loop testing, cross coverage based on
all the variables parameters and accumulated coverage across
multiple stimulation runs
For a complete listing
of features and pricing of the nSys’ PCI Express, PCI-X 2.0,
PCI-X 1.0, UART, Parallel 1284 and PCMCIA verification IP offerings,
visit the nSys web site at http://www.nsysinc.com/products.htm
Availability
The OV and OVA verification
IP offerings from nSys are available immediately. nSys OpenVera
verification IP solutions ship with full documentation and example
configurations for SoC verification environments. nSys also offers
verification consulting services for OpenVera users.
About OpenVera and
OpenVera Assertions
OpenVera is an open source hardware verification language developed
to meet the unique requirements of functional verification. OpenVera
Assertions (OVA) is a high-level language that contains powerful
declarative constructs for accurately capturing design specification
and is useful in both dynamic and formal verification environments.
With these languages, design and verification engineers describe
the target application environment, including complex protocols
and data objects, at a high level of abstraction, which significantly
improves productivity, readability and reusability. For more information
on OpenVera and OVA, visit www.open-vera.com.
About nSys
nSys provides flexible
solutions to reduce time-to-market for its customers by addressing
their verification needs for SoC development. By leveraging its
vast experience in standards-based product development, the nSys
team creates verification solutions that solve the most challenging
functional verification problems in the world. The nSys solution
is in the form of services based on specialized knowledge of standards
and tools or services backed by verification IP developed by nSys.
To learn more, visit http://www.nsysinc.com.
Synopsys is a
registered trademark of Synopsys, Inc. OpenVera is a trademark of
Synopsys, Inc. All other trademarks or registered trademarks mentioned
in this release are the intellectual property of their respective
owners.
|
