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Synopsys
Launches SystemVerilog Catalyst Program
nSys joins Synopsys
as one of the members for SystemVerilog Catalyst Program
MOUNTAIN VIEW,
Calif, October 6, 2003 - Synopsys, Inc. (Nasdaq: SNPS), the
world leader in semiconductor design software, today announced its
SystemVerilog
Catalyst Program. The SystemVerilog Catalyst Program is open
to electronic design automation (EDA) vendors, silicon and verification
intellectual property (IP) companies, and training services providers
to benefit mutual customers by advancing tool interoperability and
the availability of IP using the Accellera SystemVerilog standard.
More than 30 companies are announcing their support for SystemVerilog
at the program's launch. This broad industry support demonstrates
the rapidly growing momentum for SystemVerilog adoption by leading
design teams worldwide.
Corporate members of the SystemVerilog
Catalyst Program can gain early access to Synopsys' SystemVerilog-based
tools, such as VCS™ and HDL Compiler, the front-end language
compiler for Design Compiler™, for development and support
of their respective SystemVerilog tools, IP and training products.
By participating in the SystemVerilog Catalyst Program, member companies
can help provide their customers with a more effective path to interoperability
with Synopsys' SystemVerilog-based tools and Accellera SystemVerilog
language. Current members are 0-In Design Automation, Alatek, Aldec,
Aptix, Atrenta, Avery Design Systems, Axis Systems, Beach Solutions,
Bluespec, ChipVision, ControlNet, Doulos, Emulation and Verification
Engineering (EVE), GDA Technologies, Interra Systems, InTime, Jasper
Design Automation, Novas Software, nSys, Provis, Real Intent, Sequence
Design, SiConcepts, Silicon Interfaces, Spike Technologies, Summit
Design, Sunburst Design, Sutherland HDL, SynaptiCAD, Tenison, Tera
Systems, Tharas Systems, TNI-Valiosys, TransEDA, VeriEZ, Verific,
Verifica, Veritable, Veritools, Willamette HDL, and WSFDB Consulting,.
"SystemVerilog's enhanced
design and verification capabilities are well positioned to deliver
significant productivity and design quality benefits to the electronic
design industry,' said Aart de Geus, chairman and chief executive
officer at Synopsys, Inc. "Synopsys has a strong history of
supporting open standards and is launching the SystemVerilog Catalyst
Program to help ensure that our customers enjoy the benefits of
SystemVerilog, including increased tool and IP interoperability.
We look forward to working with current and future members of the
SystemVerilog Catalyst Program on this joint effort."
"ARM welcomes
this move by Synopsys to make its SystemVerilog-based tools more
open and accessible to the design community." said Simon Segars,
executive vice president of engineering at ARM. "ARM is actively
working with Synopsys to ensure that our IP is well placed to support
our partners who wish to take advantage of the benefits offered
by this important new language."
"0-In is actively supporting
Accellera standards. Many of 0-In's leading customers are moving
to SystemVerilog to take advantage of new design constructs,"
stated Steven D. White, president and CEO of 0-In Design Automation.
"Release V2.1 of 0-In's Assertion-Based Verification Suite,
available in Q4, will have support for the most important SystemVerilog
design constructs and we will add support for SystemVerilog assertions
in early 2004. We are working closely with Synopsys to ensure our
combined products provide the highest possible value to our customers."
"Axis Systems
continues to promote the standardization of SystemVerilog to leverage
the ability to accelerate testbench and assertions for our leading
Design Team Emulation products," said Mike Tsai, president
and chief executive officer at Axis Systems, Inc. "The SystemVerilog
Catalyst Program will enable a tighter link to development with
Synopsys' tools to provide a more complete design and verification
flow for our mutual customers."
"Novas has extended
its unified debug automation platform to support SystemVerilog design,
verification, and assertion capabilities, allowing for the fast
detection and repair of complex design problems," stated Scott
Sandler, president and CEO at Novas Software. "We're excited
to be partnering with Synopsys and other leading EDA companies to
deliver interoperable tools supporting the SystemVerilog standard,
to accelerate our customers' schedules."
About SystemVerilog
Catalyst Program
The SystemVerilog Catalyst Program is open to EDA vendors, silicon
and verification IP companies, and training services providers to
benefit mutual customers by advancing tool interoperability and
the availability of IP using the Accellera SystemVerilog standard.
SystemVerilog Catalyst Program members gain access to VCS™,
HDL Compiler™, LEDA® licenses for SystemVerilog-based
product development and mutual customer.
For moreinformation about the SystemVerilog Catalyst Program, visit http://www.synopsys.com/partners/systemverilog/systemverilog_program.html
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the world leader in EDA software
for semiconductor design. The company delivers technology-leading
semiconductor design and verification platforms to the global electronics
market, enabling the development of complex SoCs. Synopsys also
provides intellectual property and design services to simplify the
design process and accelerate time-to-market for its customers.
Synopsys is headquartered in Mountain View, California and has offices
in more than 60 locations throughout North America, Europe, Japan
and Asia. Visit Synopsys online at http://www.synopsys.com/.
VCS, Design Compiler,
and HDL Compiler are trademarks and Synopsys and LEDA are registered
trademarks of Synopsys, Inc. All other trademarks or registered
trademarks mentioned in this release are the intellectual property
of their respective owners.
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