Aldec and nSys partner to Deliver No Cost Verification IP for Evaluation

Henderson, Nevada – January 26, 2007 - Aldec, Inc., a pioneer in mixed language verification and advanced debugging tools for FPGA and ASIC devices, announced it has partnered with nSys Design Systems, the leading provider of Verilog® Verification IPs for I/O Standards. The partnership will provide the nVS (nSys Verification Suite) family of Verification IPs from nSys as encrypted Verilog based on the VSIA (Virtual Socket Interface Alliance) proposed standard at no cost evaluation for all qualified customers.

"We are pleased to be working with Aldec and look forward to a successful partnership to address the verification needs of Aldec users," stated Atul Bhatia, CEO of nSys Design Systems.

“All our Verification IPs will also be encrypted using the VSIA standard and can be simulated in Aldec’s Riviera, the only simulator that can simulate Synplicity (VSIA) encrypted RTL," added Madhur Dogra, Business Development Manager, nSys Design Systems.

“Aldec and nSys engineering teams are working together to ensure the nVS Verification IP family is validated on the Riviera mixed language simulator. Verification IP support in Riviera is a key step in our strategy to respond to the needs of our ASIC and Complex FPGA customers,“ stated David Rinehart, Vice President of Aldec, Inc.

Importance of Verification IP
The nSys Verification IPs provide a totally independent, clear and unambiguous interpretation of the specifications of a protocol for which they are designed. Typically when a totally new Verification environment and RTL are used, it has been observed that almost 50% of the bugs are in the RTL design while the other 50% of the bugs are in the Verification environment. By using the nVS family of VIPs, a developer just has to focus on the RTL bugs as the Verification environment is already proven, resulting in considerable saving of time. Since the nSys VIPs are tested with RTL designs, the user is assured inter-operability and compliance with other designs. The nVS family of proven Verification IPs is available for most commonly used I/O standards such as PCI Express, SATA, AMBA AXI, AMBA AHB & DDR2 etc.

Availability
nVS encrypted Verification IP family details are available today and can be downloaded from Aldec’s website http://www.aldec.com/products/ipcores/. The encrypted IP is supported by all Aldec’s software verification solutions operating on Unix, Windows and 32/64 bit Linux platforms. nVS is sold and supported by nSys Design Systems and its distributors, while Riviera is sold and supported by Aldec, Inc and its distributors.

About Aldec
Aldec, Inc., a 22-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX®, Linux® and Windows® platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.

About nSys
nSys is the leading provider of Verilog based Verification IPs. nSys offers the world’s largest portfolio of VIPs to its customers. nSys provides products and services to Accelerate Designs of its customers, by focusing on the verification phase of ASIC/FPGA/IP development. By leveraging its vast experience in standards-based product development, the nSys team creates verification solutions that solve the most challenging functional verification problems in the world. nSys solutions are in the form of Verification IPs backed by services.

Riviera is a trademark of Aldec, Inc. nVS is a trademark of nSys Design Systems. All other trademarks and registered trademarks are property of their respective owners.