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"We were impressed by the very strong feature set of the PCI Express nVS. Our team found the nVS to be very intuitive to use & it had good
programmable parameters providing the desired flexibility, concise and clear
documentation backed by very responsive & supportive engineering team. nSys team understood our requirement and ensured that the nVS integrated very well with our verification environment"

David Chiappini, ASIC Project Director, Matrox Graphics, Inc.

 
Popular destinations 
USB 3.0 Verification
PCI Express Gen2 Verification
SATA Verification
Ethernet Verification
 

Popular Papers 

Error Prone Areas in PCI Express designs
Migrating legacy Bus Functional Models to VMM environment
To develop or buy a Verification IP
 
Popular Success Stories 
nSys defines Verification Matrix for Matrox Graphics
JMicron PCI Express to SATA II Bridge to Success
Pericom Bridges and Switches 
 
Popular Case Studies
Independent Verification Services


Products > Verification IP: nSys Verification Suites

nSys Verification Suite (nVS) family is the world's largest portfolio of Verification IPs. Hundreds of ASIC & FPGA developers are using the nVS family to benefit from widely accepted and proven Bus Function Models, Monitor, Assertions based Checkers and Test Suites for industry standard protocols.

The nVS family has standard API as well as consistency of installation, operation and documentation resulting in customers saving time and effort spent on learning. The nVS leverages advanced verification techniques in creating a versatile testbench environment.

Option of Source code in SystemVerilog (OVM/VMM) & Verilog.

Key Benefits
Significant improvement in Verification productivity
Run basic chip-level tests in less than a week & start running full chip-level tests by end of second week
Once you know one nVS, you know how to use them all
Related Solutions
Independent Verification Services
ASIC/FPGA Design Services
SystemVerilog Migration Services
 
 
 
 
 List of nVS 

PCI family: PCI Express Gen3/ Gen2/ Gen1, SR-IOV, PCI-X, PCI

ARM AMBA: AXI, AHB, APB
Storage: SAS 3.0, SATA 3.0, ATAPI
Communications: Ethernet (100/40/10/1G), Interlaken, SPI 4.1
Consumer: USB 3.0, USB 2.0
Memory: DDR3, DDR2
Others: I2C, SMBus, SDIO, UART
 
 News 
News Bullet

nSys Announces Functional Coverage Test Suites for Major Standards/ Protocols

News Bullet

Networking & Storage Leaders Adopt 100/ 40G Ethernet Verification IP from nSys

News Bullet

nSys solves Verification IP needs for Nethra’s wide range of applications

nSys Demonstrates Verification IP for PCIe 3.0 at the PCI-SIG DevCon 2009
nSys Announces Availability of FREE Evaluation licenses of USB 3.0 Verification Suite
nSys Offers World’s Largest Portfolio Of Verification IPs For OVM-based SystemVerilog Environments 
nSys leads the way to announce PCI Express® Gen2 VIP availability in SystemVerilog
 
 Related Websites 
PCISIG
OVM World
Mentor Questa Vanguard program
Cadence Verification Alliance program
 
Events
Bullet Design, Automation & Test in Europe, 2010
March 8-12, 2010, Dresden, Germany
presenting 'Common Pitfalls in USB 3.0 Design' (Vikramjeet Singh, Design Engineer)
Bullet D&R IP-SoC Days 2010
March 23-24, 2010, Santa Clara, CA, USA
presenting 'Verification IPs for the 3rd Wave of Standards' (Atul Bhatia, CEO)
 
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